Various arithmetic operations determine the speed of the processors. Out of the other arithmetic operations, multiplication is the most time consuming. So, the aim of this paper is to design and implement a multiplier which is less time consuming and also occupies less area. This multiplier will multiply two floating point numbers (in single precision format). Here, floating point arithmetic algorithm is used but in mantissa multiplication step, rather than conventional multiplication, Booth Dadda multiplier is used. This multiplier is combination of advanced Booth multiplier and Dadda multiplier. Simulation is done using VHDL in Xilinx ISE Design suite 13.2 and is found that Booth Dadda multiplier is faster and at the same time occupies less area than other conventional multipliers.

Various arithmetic operations determine the speed of the processors. Out of the other arithmetic operations, multiplication is the most time consuming. So, the aim of this paper is to design and implement a multiplier which is less time consuming and also occupies less area. This multiplier will mul...