ورقة بحثية
مقارنة أداء الدوائر الرقمية باستخدام تقنيات الحد الأدنى لتقليل تسريب القدرة = Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Kalagadda, B.


 

مقارنة أداء الدوائر الرقمية باستخدام تقنيات الحد الأدنى لتقليل تسريب القدرة = Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Kalagadda, B.

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative...

مادة فرعية

المؤلف : Kalagadda, B.

مؤلف مشارك : N. Muthyala
Korlapati, K.K

بيانات النشر : Muscat، Sultanate of Oman : Sultan Qaboos University/ The Journal of Engineering Research، 2017مـ.

التصنيف الموضوعي : العلوم التطبيقية|الهندسة .

المواضيع : Digital Circuits .

الدوائر الرقمية .

رقم الطبعة : 1

المصدر : Sultan Qaboos University : Muscat، Sultanate of Oman.

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